In a programmable processor which fetches and executes one or more instruction words from a program memory in each cycle, in order to improve the usage of a precious program memory resource, it is generally necessary to use a fixed instruction word length. In general, each instruction differs in a required bit count X depending on the contents of operation designation for the processor.
In general, processor operation can be designated most efficiently with instruction word length X=A+B×C+D+E [bits], where A [bits] is the bit count of an opcode, B [bits] is the bit count required to express the number of registers which can be designated in an operand, C is a register count needs to be designated, D [bits] is the bit count of a flag modifying the operation of an instruction, and E [bits] is the bit count of an immediate field. Consider, for example, dyadic operation and monadic operation. The former is larger in C than the latter by one, and hence generally differs in the optimal word length X for each instruction or each instruction type.
Assume that only one type of fixed instruction word length Y is available. In this case, therefore, if X<Y concerning a given instruction, a space which is unnecessary under normal conditions is generated in the instruction word, resulting in the degraded usage of the program memory. In addition, if X>Y concerning a given instruction, the number of bits of the instruction must be decreased to match X with Y. This degrades the operation designation efficiency of the instruction for the processor. Under the circumstances, for example, Japanese Patent Laid-Open No. 8-95783 (reference 1) discloses a variable-word-length programmable processor which is provided with a predetermined basic word length and simultaneously uses a plurality of instruction word lengths of integer multiples of the basic word length.
In this case, instruction set design can be performed such that the double word length is assigned to an instruction consuming a larger bit count, and the basic word length is assigned to an instruction other than such instruction. This technique therefore improves the usage of the program memory to a certain extent and facilitates implementing a high-performance processor by increasing the degree of freedom in each instruction design without impairing the merit of a fixed instruction word length, i.e., that no gap is produced in the program memory space.
In addition, for example, Japanese Patent Laid-Open No. 5-150979 (reference 2) discloses a technique for a VLIW processor which has a dedicated instruction to designate the extension of an immediate field, instead of increasing the number of types of word lengths, in consideration of large differences between requests for the respective instructions with respect to the length of the immediate field.